Integrated circuits and other semiconductor devices may be used in environments where radiation may induce a high current event. For example, an integrated circuit in outer space or in an environment exposed to nuclear radiation may experience a transient voltage spike or a transient current spike (e.g., the high current event) caused by a collision of a high energy particle, such as a high energy proton or ion associated with cosmic radiation or nuclear radiation, with the integrated circuit. When the integrated circuit includes a metal-oxide-semiconductor field-effect transistor (MOSFET) circuit, such a collision may cause the integrated circuit (or a component thereof, such as an operational amplifier (op-amp)) to “latchup” or enter a latchup state. For example, in response to a high current event, power provided to the integrated circuit by one or more power sources may increase due to a portion of the integrated circuit acting as a low impedance path (e.g., a short) between the power rails of the integrated circuit during latchup. If the integrated circuit remains in the latchup state for an extended time period, the increased power provided to the integrated circuit may cause a latent failure to occur within the integrated circuit. A latent failure may indicate damage to the integrated circuit that does not cause an immediate error, and such damage is therefore difficult to detect. For example, a region of the integrated circuit may melt due to increased current flow through the integrated circuit, but the integrated circuit may not generate a detectable error until a later time.
Because the integrated circuit may not exit the latchup state fast enough to avoid an occurrence of a latent failure, an unprotected integrated circuit that is subject to latchup may be unsuitable for use in environments that are subject to high current events. One way to prevent a latent failure in an integrated circuit is to couple the integrated circuit to a protection circuit. Although the protection circuit may not prevent the occurrence of a latchup, the protection circuit may be configured to cause the integrated circuit experiencing latchup to exit latchup prior to occurrence of a latent failure. The protection circuit may be designed to cause the integrated circuit to exit latchup within a threshold time period (e.g., before component(s) of the integrated circuit melt). One or more characteristic values of the protection circuit, such as resistance values of resistors and capacitance values of capacitors, may be selected to prevent or reduce the likelihood of occurrence of a latent failure.
One method of predicting whether a protection circuit is likely to prevent the occurrence of latent failures is to perform a destructive physical analysis on the integrated circuit after a latchup event. The destructive physical analysis may include cutting the integrated circuit apart and studying the integrated circuit at a physical level to determine properties of the portion of the integrated circuit subject to latchup, such as a physical current path through the portion, an area of the portion, and a thermal volume associated with the portion. However, the destructive physical analysis is an irreversible and complex process, and may therefore be expensive and time-consuming.